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a
High Common-Mode Voltage, Single Supply Difference Amplifier AD8200
FUNCTIONAL BLOCK DIAGRAM SOIC (R) Package DIE Form
NC A1 A2 +VS
FEATURES High Common-Mode Voltage Range -2 V to +24 V at a 5 V Supply Voltage Operating Temperature Range Die: -40 C to +150 C 8-Lead SOIC: -40 C to +125 C Supply Voltage Range: 4.7 V to 12 V Low-Pass Filter (One Pole or Two Pole) EXCELLENT AC AND DC PERFORMANCE 15 V/ C Max Offset Drift 20 ppm/ C Max Gain Drift 80 dB CMRR Min DC to 10 kHz PLATFORMS Transmission Control Diesel Injection Control Engine Management Semi-Active Suspension Control Vehicle Dynamics Control GENERAL DESCRIPTION
+IN -IN 200k
AD8200
100k G = X10 +IN A1 -IN 200k 10k G = X2 +IN A2 -IN 10k OUT
NC = NO CONNECT
GND
The AD8200 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage. The input CMV range extends from -2 V to +24 V at a typical supply voltage of 5 V. The AD8200 is offered in die and packaged form. Both package options are specified over wide temperature ranges, making the AD8200 well suited for use in many automotive platforms. The SOIC package is specified over a temperature range of -40C to +125C. The die is specified from -40C to +150C.
Automotive platforms demand precision components for better system control. The AD8200 provides excellent ac and dc performance that keeps errors to a minimum in the user's system. Typical offset and gain drift in the SOIC package are 6 V/C and 10 ppm/C, respectively. The device also delivers a minimum CMRR of 80 dB from dc to 10 kHz. The AD8200 features an externally accessible 100 k resistor at the output of the preamp A1, which can be used for low-pass filter applications, and for establishing gains other than 20.
CLAMP DIODE
INDUCTIVE LOAD
5V OUTPUT BATTERY 14V 4 TERM SHUNT
A2
POWER DEVICE
5V OUTPUT
BATTERY
14V 4 TERM SHUNT
+IN NC +VS OUT
+IN NC +VS OUT
AD8200
-IN GND A1
AD8200
-IN GND A1 A2
POWER DEVICE CLAMP DIODE INDUCTIVE LOAD
COMMON
NC = NO CONNECT
COMMON
NC = NO CONNECT
Figure 1. High-Line Current Sensor
Figure 2. Low-Line Current Sensor
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD8200-SPECIFICATIONS
SINGLE SUPPLY (T = 25 C, V = 5 V, V
A S CM
= 0 V, RL = 10 k , Pin 5 to ground, unless otherwise noted.)
Min 20 -1 10 AD8200 SOIC Typ Max Min 20 -1 25 -1 12 AD8200 DIE Typ Max Unit
Parameter SYSTEM GAIN Initial Error vs. Temperature OFFSET VOLTAGE Offset Voltage (RTI) vs. Temperature INPUT Input Impedance Differential Common-Mode CMV Common-Mode Rejection1
Condition
VO 0.1 V dc
+1 20 +1 15
+1 30 +1 25
% ppm/C mV V/C
VCM = 0.15 V
-1 6
Continuous VCM = 10 V f = 1 kHz f = 10 kHz2
320 160 -2 80 80 10 -1 0.02 97
400 200
480 240 +24
320 160 -2 80 80 10 -1 0.02 97
400 200
480 240 +24
k k V dB dB
PREAMPLIFIER Gain Gain Error Output Voltage Range Output Resistance OUTPUT BUFFER Gain Gain Error Output Voltage Range Output Resistance DYNAMIC RESPONSE 3 dB Bandwidth Slew Rate NOISE 0.1 Hz to 10 Hz Spectral Density, 1 kHz, RTI POWER SUPPLY Operating Range Quiescent Current vs. Temp PSRR TEMPERATURE RANGE For Specified Performance
100 2
+1 4.8 103
100 2
+1 4.8 103
% V k
-1 0.02 2 30 50 0.22 10 300 4.7 VO = 0.1 V dc VS = 4.7 V to 12 V 75 -40 0.25 80
+1 4.8
-1 0.02 2 30 50 0.22 10 300
+1 4.8
% V kHz V/s V p-p nV/Hz
12 1
4.7 75 0.25 80
12 1
V mA dB C
+125
-40
+150
NOTES 1 Source Imbalance < 2 . 2 The AD8200 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 k resistor, even the small amounts of pinto-pin capacitance between Pins 1, 8 and 3, 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-topin coupling may be neglected in all applications using filter capacitors at Node 3. Specifications subject to change without notice.
-2-
REV. 0
AD8200
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 V Transient Input Voltage (300 ms) . . . . . . . . . . . . . . . . . . 44 V Continuous Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 35 V Reversed Supply Voltage Protection . . . . . . . . . . . . . . . 0.3 V Operating Temperature . . . . . . . . . . . (Die) -40C to +150C . . . . . . . . . (SOIC) -40C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300C
*Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-IN 1 GND 2
8
+IN
NC TOP VIEW A1 3 (Not to Scale) 6 +VS
7
AD8200
A2 4
5
OUT
NC = NO CONNECT
ORDERING GUIDE
Model AD8200R AD8200CHIPS
Temperature Range -40C to +125C -40C to +150C
Package Description Plastic SOIC
Package Option SO-8 DIE Form
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
METALLIZATION PHOTOGRAPH
+VS
6
5 +IN 8
OUT
-IN
1
4
A2
2
3
GND
A1
REV. 0
-3-
AD8200-Typical Performance Characteristics noted.)
30 0
(TA = 25 C, VS = 5 V, VCM = 0 V, RL = 10 k
unless otherwise
30
NEGATIVE COMMON-MODE RANGE - Volts
POSITIVE COMMON-MODE RANGE - Volts
25 20 15
GAIN - dB
25
+VCM
-2
20
-4
10 5 0 -5 -10 -15 -20 1k 10k 100k FREQUENCY - Hz 1M
15 -VCM
-6
10
-8
5
-10
0 2 3 4 SUPPLY VOLTAGE - Volts 5
-12
TPC 1. Input Common-Mode Range vs. Supply
TPC 4. Gain vs. Frequency
0 -5 RL =
100 95 90 85
OUTPUT VOLTAGE - mV
-10
CMRR - dB
RL = 10k TO GND 2
-15
80 75 70 65 60 55
-20 -25
-30 -35
4 3 SUPPLY VOLTAGE - Volts
5
50 10
100
1k 10k FREQUENCY - Hz
100k
1M
TPC 2. Output Voltage - VS vs. Supply
TPC 5. Common-Mode Rejection vs. Frequency
5
100 90
4
OUTPUT VOLTAGE - Volts
80 70
PSRR - dB
3
60 50 40 30
2
1
20 10
0 10
100 1k LOAD RESISTANCE -
10k
0 10
100
1k FREQUENCY - Hz
10k
100k
TPC 3. Output Voltage Swing vs. Load Resistance
TPC 6. Power Supply Rejection vs. Frequency
-4-
REV. 0
AD8200
TEK RUN: 2.5MS/s HI RES
TEK RUN: 2.5MS/s AVERAGE
VOUT, RL = 10k
1 VOUT, RL = 10k
1
T VIN
MAGNIFIED VOUT 3 2 VIN CH1 1V CH 2 10mV M 20 s CH1 CH3 100mV 1.36V
2 CH1 500mV CH2 50mV M 20 s CH1 1.5V
TPC 7. Pulse Response
TPC 8. Settling Time
THEORY OF OPERATION
The AD8200 consists of a preamp and buffer arranged as shown in Figure 3. Like-named resistors have equal values. The preamp incorporates a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of RA, RB, RC, and RG, attenuate input signals applied to Pins 1 and 8. Note that when equal amplitude signals are asserted at inputs 1 and 8, and the output of A1 is equal to the common potential (i.e., zero), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A1 and thus its output, will be zero. Any common-mode voltage applied to both inputs will keep the bridge balanced and the A1 output at zero. Because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state. However, if the signals applied to the inputs differ, the result is a difference at the input to A1. A1 responds by adjusting its output to drive RB, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. By attenuating voltages at Pins 1 and 8, the amplifier inputs are held within the power supply range, even if Pin 1 and Pin 8 input levels exceed the supply, or fall below Common (Ground.) The input network also attenuates normal (differential) mode voltages. RC and RG form an attenuator that scales A1 feedback, forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at ten. Because the differential input signal is attenuated, and then amplified to yield an overall gain of ten, the amplifier A1 operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pins 1 and 8.
+IN -IN
To minimize these errors while extending the common-mode range, a dedicated feedback loop is employed to reduce the range of common-mode voltage applied to A1, for a given overall range at the inputs. By offsetting the range of voltage applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. Amplifier A3 detects the common-mode signal applied to A1 and adjusts the voltage on the matched RCM resistors to reduce the common-mode voltage range at the A1 inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. The output of the dynamic bridge taken from A1 is connected to Pin 3 by way of a 100 k series resistor, provided for lowpass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. The output of the preamp drives a gain-of-two buffer-amplifier A2, implemented with carefully matched feedback resistors RF. The two-stage system architecture of the AD8200 enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale rail-to-rail signal from the preamp can be filtered at Pin 3, and a half-scale signal resulting from filtering can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of A2 is approximately 100 k, to minimize the effects of A2's input bias current. However, this current is quite small and errors resulting from applications that mismatch the resistance are correspondingly small.
APPLICATIONS
RA
RA 100k A1 (TRIMMED) RCM RCM A3 RF RG A2 RF
The AD8200 difference amplifier is intended for applications where it is required to extract a small differential signal in the presence of large common-mode voltages. The input resistance is nominally 200 k, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. The open collector output stage will source current to within 20 mV of ground.
RB RG RC
RB RC
AD8200
COM
Figure 3. Simplified Schematic
REV. 0
-5-
AD8200
CURRENT SENSING High-Line, High-Current Sensing Gains Greater than 20
Basic automotive applications making use of the large commonmode range are shown in Figures 1 and 2. The capability of the device to operate as an amplifier in primary battery supply circuits is shown in Figure 1, Figure 2 illustrates the ability of the device to withstand voltages below system ground.
Low Current Sensing
The AD8200 can also be used in low current sensing applications, such as a 4-20 mA current loop shown in Figure 4. In such applications, the relatively large shunt resistor can degrade the common-mode rejection. Adding a resistor of equal value in the low-impedance side of the input corrects for this error.
10 1%
+IN NC +VS OUT
Connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in Figure 6, will increase the gain. The gain is now multiplied by the factor REXT/(REXT - 100 k); for example, it is doubled for REXT = 200 k. Overall gains as high as 50 are achievable in this way. Note that the accuracy of the gain becomes critically dependent on resistor value at high gains. Also, the effective input offset voltage at Pins 1 and 8 (about six times the actual offset of A1) limits the part's use in very high-gain, dc-coupled applications.
+VS OUT
+IN NC +VS OUT
5V OUTPUT
VDIFF 2 VDIFF 2
10k
10k GAIN = REXT
20REXT REXT - 100k GAIN GAIN - 20
AD8200
VCM 100k
+
10 1%
REXT = 100k
AD8200
-IN GND A1 A2
-IN
GND
A1
A2
NC = NO CONNECT
Figure 6. Adjusting for Gains Greater than 20
NC = NO CONNECT
GAIN TRIM
Figure 4. 4-20 mA Current Loop Receiver
GAIN ADJUSTMENT
Figure 7 shows a method for incremental gain trimming using a trimpot and external resistor REXT. The following approximation is useful for small gain ranges: G (10 M / REXT) % Thus, the adjustment range would be 2% for REXT = 5 M; 10% for REXT = 1 M, etc.
5V OUT VDIFF 2 VDIFF 2
The default gain of the preamplifier and buffer are x10 and x2 respectively, resulting in a composite gain of x20. With the addition of external resistor(s) or trimmer(s), the gain may be lowered, raised, or finely calibrated.
Gains Less than 20
See Figure 5. Since the preamplifier has an output resistance of 100 k, an external resistor connected from Pins 3 and 4 to GND will decrease the gain by a factor REXT/(100 k + REXT).
+VS OUT
VCM
+IN NC +VS OUT
+IN
NC +VS OUT
AD8200
-IN GND A1 A2
VDIFF 2 VDIFF 2
10k
10k GAIN =
20REXT REXT + 100k GAIN 20 - GAIN
NC = NO CONNECT
REXT
GAIN TRIM 20k MIN
AD8200
VCM 100k
REXT = 100k
-IN
GND
A1
A2
Figure 7. Incremental Gain Trim
REXT NC = NO CONNECT
Figure 5. Adjusting for Gains Less than 20
The overall bandwidth is unaffected by changes in gain using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. In many cases this can be ignored, but if desired, can be nulled by inserting a resistor equal to 100 k minus the parallel sum of REXT and 100 k, in series with Pin 4. For example, with REXT = 100 k (yielding a composite gain of x10), the optional offset nulling resistor is 50 k (see Figure 11.) -6- REV. 0
AD8200
Internal Signal Overload Considerations
5V OUT VDIFF 2 VDIFF 2
When configuring gain for values other than 20, the maximum input voltage with respect to the supply voltage and ground must be considered, since either the preamplifier or the output buffer will reach its full-scale output (approximately VS - 0.2 V) with large differential input voltages. The input of the AD8200 is limited to (VS - 0.2) / 10, for overall gains 10, since the preamplifier, with its fixed gain of x10, reaches its full-scale output before the output buffer. For gains greater than 10, the swing at the buffer output reaches its full-scale first and limits the AD8200 input to (VS - 0.2) / G, where G is the overall gain.
LOW-PASS FILTERING
+IN NC +VS OUT
AD8200
VCM
-IN GND A1 A2
C
255k C NC = NO CONNECT FC = 1Hz - F
In many transducer applications it is necessary to filter the signal to remove spurious high-frequency components, including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14. Signals having large spikes may have PARs of 10 or more. When implementing a filter, the PAR should be considered so the output of the AD8200 preamplifier (A1) does not clip before A2, since this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should be made to clip at the same time. This condition is achieved when the PAR, is no greater than the gain of the second amplifier (2 for the default configuration). For example, if a PAR of 5 is expected, the gain of A2 should be increased to 5. Low-pass filters can be implemented in several ways using the features provided by the AD8200. In the simplest case, a singlepole filter (20 dB/decade) is formed when the output of A1 is connected to the input of A2 via the internal 100 k resistor by strapping Pins 3 and 4, and a capacitor added from this node to ground, as shown in Figure 8. If a resistor is added across the capacitor to lower the gain, the corner frequency will increase; it should be calculated using the parallel sum of the resistor and 100 k.
5V OUT VDIFF 2 VDIFF 2
Figure 9. 2-Pole Low-Pass Filter
A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented using the connections shown in Figure 9. This is a Sallen-Key form based on a x2 amplifier. It is useful to remember that a 2-pole filter with a corner frequency f2 and a 1-pole filter with a corner at f1 have the same attenuation at the frequency (f22/f1). The attenuation at that frequency is 40 Log (f2/f1). This is illustrated in Figure 10. Using the standard resistor value shown, and equal capacitors (Figure 9), the corner frequency is conveniently scaled at 1 Hz-F (0.05 F for a 20 Hz corner). A maximally flat response occurs when the resistor is lowered to 196 k and the scaling is then 1.145 Hz-F. The output offset is raised by about 5 mV (equivalent to 250 V at the input pins).
FREQUENCY
ATTENUATION
40dB/DECADE 20dB/DECADE
40LOG (f2/f1)
+IN NC +VS OUT
AD8200
VCM
-IN GND A1 A2
FC =
1 2 C105
A 1-POLE FILTER, CORNER f1, AND A 2-POLE FILTER, CORNER f2, HAVE THE SAME ATTENUATION -40LOG (f2/f1) AT FREQUENCY f22/f1 f1 f2 f22/f1
C IN FARADS
Figure 10. Comparative Responses of 1- and 2-Pole LowPass Filters
C
NC = NO CONNECT
Figure 8. A Single-Pole, Low-Pass Filter Using the Internal 100 k Resistor
If the gain is raised using a resistor, as shown in Figure 8, the corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of 200 k (for which the gain would be doubled) the corner frequency is now 0.796 Hz-F, (0.039 F for a 20 Hz corner frequency.)
REV. 0
-7-
AD8200
HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT DRIVING CHARGE REDISTRIBUTION A/D CONVERTERS
Figure 11 is another refinement of Figure 1, including gain adjustment and low-pass filtering.
INDUCTIVE LOAD
+IN
BATTERY
14V 4 TERM SHUNT
NC +VS OUT
191k
AD8200
-IN GND A1 A2
20k
POWER DEVICE
VOS/IB NULL C
NC = NO CONNECT
COMMON
5% CALIBRATION RANGE FC = 0.796Hz - F (0.22 F FOR f = 3.6 Hz)
Figure 11. High-Line Current Sensor Interface. Gain = x40, Single-Pole, Low-Pass Filter
Since the perturbations from the analog-to-digital converter are small, the output impedance of the AD8200 will appear to be low. The transient response will, therefore, have a time constant governed by the product of the two LAG components, CLAG x RLAG. For the values shown in Figure 13, this time constant is programmed at approximately 10 s. Therefore, if samples are taken at several tens of microseconds or more, there will be negligible charge "stack-up."
5V
A power device that is either `ON' or `OFF' controls the current in the load. The average current is proportional to the duty cycle of the input pulse, and is sensed by a small value resistor. The average differential voltage across the shunt is typically 100 mV, although its peak value will be higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, on the other hand, extends from roughly 1 V above ground, when the switch is `ON,' to about 1.5 V above the battery voltage, when the device is `OFF,' and the clamp diode conducts. If the maximum battery voltage spikes up to 20 V, the common-mode voltage at the input can be as high as 21.5 V. To produce a full-scale output of 4 V, a gain x40 is used, adjustable by 5% to absorb the tolerance in the shunt. There is sufficient headroom to allow 10% overrange (to 4.4 V). The roughly triangular voltage across the sense resistor is averaged by a single-pole, low-pass filter, here set with a corner frequency = 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A higher rate of attenuation can be obtained using a two-pole filter having fC = 20 Hz, as shown in Figure 12. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the single-pole filter.
INDUCTIVE LOAD
AD8200
+IN A2 RLAG 1k CLAG 0.01 F PROCESSOR A/D
-IN
10k
10k
Figure 13. Recommended Circuit for Driving CMOS A /D
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
CLAMP DIODE
5V OUTPUT
8-Lead SOIC Package (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
BATTERY
14V 4 TERM SHUNT
+IN NC +VS OUT
432k C
AD8200
-IN GND A1 A2
50k
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
POWER DEVICE
127k C
0.0500 (1.27) BSC FC = 1Hz - F (0.05 F FOR fC = 20Hz) 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
NC = NO CONNECT
COMMON
Figure 12. Illustration of 2-Pole Low-Pass Filtering
0.0500 (1.27) 0.0160 (0.41)
-8-
REV. 0
PRINTED IN U.S.A.
C02054-4.5-10/00 (rev. 0)
CLAMP DIODE
5V
OUTPUT 4V/AMP
When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection ( Q) can cause a significant deflection in the output voltage of the AD8200. Though generally of short duration, this deflection may persist until after the sample period of the ADC has expired, due to the relatively high open-loop output impedance of the AD8200. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high-frequency output impedance of the AD8200. For these applications, the output signal should be taken from the midpoint of the RLAG-CLAG combination as shown in Figure 13.

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